Invention Grant
US08694877B2 Max-log-map equivalence log likelihood ratio generation soft viterbi architecture system and method
有权
最大对数映射等价对数似然比生成软维特比架构系统和方法
- Patent Title: Max-log-map equivalence log likelihood ratio generation soft viterbi architecture system and method
- Patent Title (中): 最大对数映射等价对数似然比生成软维特比架构系统和方法
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Application No.: US12924707Application Date: 2010-10-01
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Publication No.: US08694877B2Publication Date: 2014-04-08
- Inventor: Sivagnanam Parthasarathy , Lun Bin Huang , Alessandro Risso
- Applicant: Sivagnanam Parthasarathy , Lun Bin Huang , Alessandro Risso
- Applicant Address: US TX Coppell
- Assignee: STMicroelectronics, Inc.
- Current Assignee: STMicroelectronics, Inc.
- Current Assignee Address: US TX Coppell
- Agency: Graybeal Jackson LLP
- Main IPC: H03M13/03
- IPC: H03M13/03

Abstract:
A modified soft output Viterbi algorithm (SOVA) detector receives a sequence of soft information values and determines a best path and an alternate path for each soft information value and further determines, when the best and alternate paths lead to the same value for a given soft information value, whether there is a third path departing from the alternate path that leads to an opposite decision with respect to the best path for a given soft information value. The SOVA detector then considers this third path when updating the reliability of the best path. The modified SOVA detector achieves max-log-map equivalence effectively through the Fossorier approach and includes modified reliability metric units for the first N stages of the SOVA detector, where N is the memory depth of a given path, and includes conventional reliability metric units for the remaining stages of the detector.
Public/Granted literature
- US20110197112A1 Max-log-map equivalence log likelihood ratio generation soft Viterbi architecture system and method Public/Granted day:2011-08-11
Information query
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