Invention Grant
US08698128B2 Gate-all around semiconductor nanowire FET's on bulk semicoductor wafers
有权
半导体纳米线FET围绕散装半导体晶圆的栅极
- Patent Title: Gate-all around semiconductor nanowire FET's on bulk semicoductor wafers
- Patent Title (中): 半导体纳米线FET围绕散装半导体晶圆的栅极
-
Application No.: US13405682Application Date: 2012-02-27
-
Publication No.: US08698128B2Publication Date: 2014-04-15
- Inventor: Jeffrey W. Sleight , Josephine B. Chang , Isaac Lauer , Shreesh Narasimha
- Applicant: Jeffrey W. Sleight , Josephine B. Chang , Isaac Lauer , Shreesh Narasimha
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent H. Daniel Schnurmann
- Main IPC: H01L29/775
- IPC: H01L29/775

Abstract:
Non-planar semiconductor devices are provided that include at least one semiconductor nanowire suspended above a semiconductor oxide layer that is present on a first portion of a bulk semiconductor substrate. An end segment of the at least one semiconductor nanowire is attached to a first semiconductor pad region and another end segment of the at least one semiconductor nanowire is attached to a second semiconductor pad region. The first and second pad regions are located above and are in direct contact with a second portion of the bulk semiconductor substrate which is vertically offsets from the first portion. The structure further includes a gate surrounding a central portion of the at least one semiconductor nanowire, a source region located on a first side of the gate, and a drain region located on a second side of the gate which is opposite the first side of the gate.
Public/Granted literature
- US20130221319A1 Gate-All Around Semiconductor Nanowire FET's On Bulk Semicoductor Wafers Public/Granted day:2013-08-29
Information query
IPC分类: