Invention Grant
US08699281B2 Semiconductor memory device and method with auxiliary I/O line assist circuit and functionality
有权
具有辅助I / O线辅助电路和功能的半导体存储器件和方法
- Patent Title: Semiconductor memory device and method with auxiliary I/O line assist circuit and functionality
- Patent Title (中): 具有辅助I / O线辅助电路和功能的半导体存储器件和方法
-
Application No.: US13550783Application Date: 2012-07-17
-
Publication No.: US08699281B2Publication Date: 2014-04-15
- Inventor: Shetti Shanmukheshwara Rao , Ankur Goel
- Applicant: Shetti Shanmukheshwara Rao , Ankur Goel
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory Inc.
- Current Assignee: Elpida Memory Inc.
- Current Assignee Address: JP Tokyo
- Agency: McGinn IP Law Group, PLLC
- Priority: IN1999/CHE/2008 20080818
- Main IPC: G11C7/10
- IPC: G11C7/10

Abstract:
A semiconductor memory device includes an I/O line for transmitting read data that has been read from a memory cell, a plurality of driver circuits for driving the I/O line on the basis of the read data, a read circuit for receiving the read data transmitted through the I/O line, and an assist circuit for amplifying the read data transmitted through the I/O line. The assist circuit is disposed farther away from a prescribed drive circuit included in the plurality of drive circuits as viewed from the read circuit. The signal level can thereby rapidly change levels even in memories having relatively long I/O lines.
Public/Granted literature
- US20120281486A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD WITH AUXILIARY I/O LINE ASSIST CIRCUIT AND FUNCTIONALITY Public/Granted day:2012-11-08
Information query