Invention Grant
US08699559B2 Decision feedback equalization scheme with minimum correction delay
有权
具有最小校正延迟的判决反馈均衡方案
- Patent Title: Decision feedback equalization scheme with minimum correction delay
- Patent Title (中): 具有最小校正延迟的判决反馈均衡方案
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Application No.: US13772872Application Date: 2013-02-21
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Publication No.: US08699559B2Publication Date: 2014-04-15
- Inventor: Simone Erba , Massimo Pozzoni
- Applicant: STMicroelectronics S.R.L.
- Applicant Address: IT Agrate Brianza (MB)
- Assignee: STMicroelectronics S.R.L.
- Current Assignee: STMicroelectronics S.R.L.
- Current Assignee Address: IT Agrate Brianza (MB)
- Agency: Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.
- Priority: ITVA2008A0053 20081024
- Main IPC: H04B1/38
- IPC: H04B1/38

Abstract:
A decision feedback equalizer includes a correction circuit to correct a sampled value of an incoming bit based on intersymbol interference of at least one preceding bit, and to generate a received bit. The correction circuit includes a first multiplexer and a first pair of latches coupled thereto. The first multiplexer is controlled by a clock signal to generate a digital level representative of a sign of a first correction coefficient to be subtracted from the sampled value of the incoming bit for deleting the intersymbol interference. The first pair of latches receives as input the received bit and is clocked in phase opposition by the clock signal to generate respective latched replicas of the received bit during respective active phases of the clock signal. The respective latched replicas are input to the first multiplexer.
Public/Granted literature
- US20130156087A1 A DECISION FEEDBACK EQUALIZATION SCHEME WITH MINIMUM CORRECTION DELAY Public/Granted day:2013-06-20
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