Invention Grant
US08700943B2 Controlling time stamp counter (TSC) offsets for mulitple cores and threads
有权
控制多个内核和线程的时间戳计数器（TSC）偏移量
- Patent Title: Controlling time stamp counter (TSC) offsets for mulitple cores and threads
- Patent Title (中): 控制多个内核和线程的时间戳计数器（TSC）偏移量
-
Application No.: US12644989Application Date: 2009-12-22
-
Publication No.: US08700943B2Publication Date: 2014-04-15
- Inventor: Martin G. Dixon , Jeremy J. Shrall , Rajesh S. Parthasarathy
- Applicant: Martin G. Dixon , Jeremy J. Shrall , Rajesh S. Parthasarathy
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F1/12
- IPC: G06F1/12 ; G06F15/16
Abstract:
In one embodiment, the present invention includes a method for recording a time stamp counter (TSC) value of a first TSC counter of a processor before a system suspension, accessing the stored TSC value after the system suspension, and directly updating a thread offset value associated with a first thread executing on a first core of the processor with the stored TSC value, without performing a synchronization between a plurality of cores of the processor. Other embodiments are described and claimed.
Public/Granted literature
- US20110154090A1 Controlling Time Stamp Counter (TSC) Offsets For Mulitple Cores And Threads Public/Granted day:2011-06-23
Information query
