Invention Grant
US08700955B2 Multi-processor data processing system having synchronized exit from debug mode and method therefor
有权
具有从调试模式同步退出的多处理器数据处理系统及其方法
- Patent Title: Multi-processor data processing system having synchronized exit from debug mode and method therefor
- Patent Title (中): 具有从调试模式同步退出的多处理器数据处理系统及其方法
-
Application No.: US13239649Application Date: 2011-09-22
-
Publication No.: US08700955B2Publication Date: 2014-04-15
- Inventor: William C. Moyer , Jimmy Gumulja , Gary L. Miller
- Applicant: William C. Moyer , Jimmy Gumulja , Gary L. Miller
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Daniel D. Hill
- Main IPC: G06F11/00
- IPC: G06F11/00
Abstract:
A data processing system includes a plurality of data processors, debug logic, and linking logic. The debug logic is coupled to each data processor of the plurality of data processors, and is for providing an instruction for exiting debug mode to the plurality of data processors. The linking logic is coupled to the debug logic and to each of the plurality of data processors. The linking logic is for linking selected ones of the plurality of data processors with each other and to the debug logic. The debug logic provides the instruction for exiting the debug mode when the selected ones of the plurality of data processors are linked in parallel by the linking logic.
Public/Granted literature
- US20130080748A1 MULTI-PROCESSOR DATA PROCESSING SYSTEM HAVING SYNCHRONIZED EXIT FROM DEBUG MODE AND METHOD THEREFOR Public/Granted day:2013-03-28
Information query
