Invention Grant
- Patent Title: Parallel residue arithmetic operation unit and parallel residue arithmetic operating method
- Patent Title (中): 并行残差算术运算单元和并行残差运算法
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Application No.: US12377772Application Date: 2007-08-21
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Publication No.: US08700971B2Publication Date: 2014-04-15
- Inventor: Hiroyuki Motozuka
- Applicant: Hiroyuki Motozuka
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: Greenblum & Bernstein, P.L.C.
- Priority: JP2006-225934 20060822
- International Application: PCT/JP2007/066156 WO 20070821
- International Announcement: WO2008/023684 WO 20080228
- Main IPC: H03M13/00
- IPC: H03M13/00

Abstract:
A parallel residue arithmetic operation unit is provided to reduce processing delay, and to make an additional multiplier or a residue arithmetic circuit unnecessary, so that a circuit can become small in size. In the parallel residue arithmetic operation unit, a parallel CRC calculation circuit includes input terminals to which input data are divided into a plurality of sub-blocks and the sub-blocks are input in parallel, an initial value generating unit for generating a part CRC corresponding to the forefront of each sub-block as an initial value, a part CRC generating unit for receiving the part CRC corresponding to the forefront of each sub-block as the initial value and sequentially generating a residue part CRC in accordance with a recurrent equation, AND units for calculating logical multiplications of part CRC values, and a cumulative adding unit for cumulatively adding values output from the AND units.
Public/Granted literature
- US20100198892A1 PARALLEL RESIDUE ARITHMETIC OPERATION UNIT AND PARALLEL RESIDUE ARITHMETIC OPERATING METHOD Public/Granted day:2010-08-05
Information query
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