Invention Grant
US08701062B2 Apparatus and method for generating a netlist using non-uniquified module during logic synthesis stage 有权
用于在逻辑合成阶段期间使用非唯一模块生成网表的装置和方法

  • Patent Title: Apparatus and method for generating a netlist using non-uniquified module during logic synthesis stage
  • Patent Title (中): 用于在逻辑合成阶段期间使用非唯一模块生成网表的装置和方法
  • Application No.: US13211375
    Application Date: 2011-08-17
  • Publication No.: US08701062B2
    Publication Date: 2014-04-15
  • Inventor: Mitsuyoshi Fujiwara
  • Applicant: Mitsuyoshi Fujiwara
  • Applicant Address: JP Kawasaki
  • Assignee: Fujitsu Limited
  • Current Assignee: Fujitsu Limited
  • Current Assignee Address: JP Kawasaki
  • Agency: Fujitsu Patent Center
  • Priority: JP2010-196195 20100901
  • Main IPC: G06F17/50
  • IPC: G06F17/50
Apparatus and method for generating a netlist using non-uniquified module during logic synthesis stage
Abstract:
A netlist generating apparatus including a memory configured to store logic design data and a processor configured to execute an operation. The operation including selecting paths with which names of instances after logic synthesis match names of modules before being uniquified during the logic synthesis by referring to violation data for paths of the instances and a correspondence table in which the modules are associated with paths of the instances, extracting a path with worst violation data from selected paths by comparing violation data of the selected paths, and adjusting a timing of the extracted path with the worst violation data and generating a netlist.
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