Invention Grant
- Patent Title: Integrated circuit packaging system with warpage preventing mechanism and method of manufacture thereof
- Patent Title (中): 具有防翘曲机构的集成电路封装系统及其制造方法
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Application No.: US13490908Application Date: 2012-06-07
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Publication No.: US08703535B2Publication Date: 2014-04-22
- Inventor: MinJung Kim , DaeSik Choi , MinWook Yu , YiSu Park
- Applicant: MinJung Kim , DaeSik Choi , MinWook Yu , YiSu Park
- Applicant Address: SG Singapore
- Assignee: Stats Chippac Ltd.
- Current Assignee: Stats Chippac Ltd.
- Current Assignee Address: SG Singapore
- Agency: Ishimaru & Associates LLP
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a warpage-compensation zone with a substrate-interior layer exposed from a top substrate-cover, and the warpage-compensation zone having contiguous exposed portion of the substrate-interior layer over corner portions of the package substrate; connecting an integrated circuit die to the package substrate with an internal interconnect; and forming an encapsulation over the integrated circuit die, with the encapsulation directly on the substrate-interior layer in the warpage-compensation zone.
Public/Granted literature
- US20130328179A1 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WARPAGE PREVENTING MECHANISM AND METHOD OF MANUFACTURE THEREOF Public/Granted day:2013-12-12
Information query
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