Invention Grant
- Patent Title: N/P boundary effect reduction for metal gate transistors
- Patent Title (中): 金属栅极晶体管的N / P边界效应降低
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Application No.: US13299152Application Date: 2011-11-17
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Publication No.: US08703595B2Publication Date: 2014-04-22
- Inventor: Hak-Lay Chuang , Cheng-Cheng Kuo , Ching-Che Tsai , Ming Zhu , Bao-Ru Young
- Applicant: Hak-Lay Chuang , Cheng-Cheng Kuo , Ching-Che Tsai , Ming Zhu , Bao-Ru Young
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/336
- IPC: H01L21/336
Abstract:
The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a plurality of dummy gates over a substrate. The dummy gates extend along a first axis. The method includes forming a masking layer over the dummy gates. The masking layer defines an elongate opening extending along a second axis different from the first axis. The opening exposes first portions of the dummy gates and protects second portions of the dummy gates. A tip portion of the opening has a width greater than a width of a non-tip portion of the opening. The masking layer is formed using an optical proximity correction (OPC) process. The method includes replacing the first portions of the dummy gates with a plurality of first metal gates. The method includes replacing the second portions of the dummy gates with a plurality of second metal gates different from the first metal gates.
Public/Granted literature
- US20130126977A1 N/P BOUNDARY EFFECT REDUCTION FOR METAL GATE TRANSISTORS Public/Granted day:2013-05-23
Information query
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