Invention Grant
US08703606B2 Method for manufacturing semiconductor device having a wiring structure
有权
具有布线结构的半导体器件的制造方法
- Patent Title: Method for manufacturing semiconductor device having a wiring structure
- Patent Title (中): 具有布线结构的半导体器件的制造方法
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Application No.: US13363931Application Date: 2012-02-01
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Publication No.: US08703606B2Publication Date: 2014-04-22
- Inventor: Tomoyuki Kirimura
- Applicant: Tomoyuki Kirimura
- Applicant Address: JP Yokohama
- Assignee: Fujitsu Semiconductor Limited
- Current Assignee: Fujitsu Semiconductor Limited
- Current Assignee Address: JP Yokohama
- Agency: Westerman, Hattori, Daniels & Adrian, LLP
- Main IPC: H01L23/528
- IPC: H01L23/528

Abstract:
When a wiring structure is formed by a trench-first dual damascene method, a first hard mask for forming via holes and a second hard mask for forming wiring trenches are sequentially formed on an interlayer insulating film, openings are formed at the first hard mask while using the second hard mask as a mask, and thereafter, the openings are expanded in a lateral direction by an isotropic etching to form openings, via holes are formed by etching the interlayer insulating film while using the first hard mask and the second hard mask as masks, and wiring trenches communicating with the via holes are formed by etching the interlayer insulating film while using the second hard mask as a mask.
Public/Granted literature
- US20120129338A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Public/Granted day:2012-05-24
Information query
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