Invention Grant
US08704286B2 Method and structure for integrating capacitor-less memory cell with logic
有权
将无电容器存储单元与逻辑集成的方法和结构
- Patent Title: Method and structure for integrating capacitor-less memory cell with logic
- Patent Title (中): 将无电容器存储单元与逻辑集成的方法和结构
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Application No.: US13610053Application Date: 2012-09-11
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Publication No.: US08704286B2Publication Date: 2014-04-22
- Inventor: Gurtej S. Sandhu
- Applicant: Gurtej S. Sandhu
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John, P.S.
- Main IPC: H01L29/76
- IPC: H01L29/76
Abstract:
Methods for fabricating integrated circuits include fabricating a logic device on a substrate, forming an intermediate semiconductor substrate on a surface of the logic device, and fabricating a capacitor-less memory cell on the intermediate semiconductor substrate. Integrated circuits with capacitor-less memory cells formed on a surface of a logic device are also disclosed, as are multi-core microprocessors including such integrated circuits.
Public/Granted literature
- US20130003452A1 Method and Structure for Integrating Capacitor-less Memory Cell with Logic Public/Granted day:2013-01-03
Information query
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