Invention Grant
- Patent Title: PLL circuit
- Patent Title (中): PLL电路
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Application No.: US13780936Application Date: 2013-02-28
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Publication No.: US08704564B2Publication Date: 2014-04-22
- Inventor: Kazuki Hasegawa , Shunichiro Masaki
- Applicant: Fujitsu Semiconductor Limited
- Applicant Address: JP Yokohama
- Assignee: Fujitsu Semiconductor Limited
- Current Assignee: Fujitsu Semiconductor Limited
- Current Assignee Address: JP Yokohama
- Agency: Arent Fox LLP
- Priority: JP2012-092863 20120416
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
A PLL circuit includes a low-pass filter configured to generate a control voltage according to an output current from a charge pump. The low-pass filter includes a preceding stage circuit portion configured to store electric charges according to the output current from the charge pump, and a succeeding stage circuit portion configured to generate the control voltage by receiving the electric charges stored in and transferred from the preceding stage circuit portion. Also, the preceding stage circuit portion includes plural charge storage circuits each including a capacitor, a first switch connected between the capacitor and the charge pump and configured to be driven by a first switch control signal, and a second switch connected between the capacitor and the succeeding stage circuit portion and configured to be driven by a second switch control signal.
Public/Granted literature
- US20130271191A1 PLL CIRCUIT Public/Granted day:2013-10-17
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