Invention Grant
- Patent Title: Semiconductor device having dummy bit lines wider than bit lines
- Patent Title (中): 具有比位线宽的虚拟位线的半导体器件
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Application No.: US13560137Application Date: 2012-07-27
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Publication No.: US08705261B2Publication Date: 2014-04-22
- Inventor: Eiji Ito , Hideyuki Kinoshita , Tetsuya Kamigaki , Koji Hashimoto
- Applicant: Eiji Ito , Hideyuki Kinoshita , Tetsuya Kamigaki , Koji Hashimoto
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2005-176581 20050616
- Main IPC: G11C5/06
- IPC: G11C5/06

Abstract:
A method of manufacturing a semiconductor device includes forming a plurality of dummy line patterns arranged at a first pitch on an underlying region, forming first mask patterns having predetermined mask portions formed on long sides of the dummy line patterns, each of the first mask patterns having a closed-loop shape and surrounding each of the dummy line patterns, removing the dummy line patterns, forming a second mask pattern having a first pattern portion which covers end portions of the first mask patterns and inter-end portions each located between adjacent ones of the end portions, etching the underlying region using the first mask patterns and the second mask pattern as a mask to form trenches each located between adjacent ones of the predetermined mask portions, and filling the trenches with a predetermined material.
Public/Granted literature
- US20120292764A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Public/Granted day:2012-11-22
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