Invention Grant
- Patent Title: Memory controller and control method
- Patent Title (中): 内存控制器和控制方式
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Application No.: US13454200Application Date: 2012-04-24
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Publication No.: US08705296B2Publication Date: 2014-04-22
- Inventor: Shinya Aiso
- Applicant: Shinya Aiso
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki
- Agency: Staas & Halsey LLP
- Priority: JP2011-124767 20110603
- Main IPC: G11C7/00
- IPC: G11C7/00
Abstract:
A memory controller includes: a first write circuit configured to write a first dummy pattern including a plurality of consecutive first dummy values at a first address of a memory; a second write circuit configured to write a first pattern including a plurality of types of consecutive values at a second address of the memory after a write operation of the first dummy pattern by the first write circuit; a third write circuit configured to write a second dummy pattern including a plurality of consecutive second dummy values at a third address of the memory after a write operation of the first pattern by the second write circuit; a read circuit configured to read the written first pattern based on the second address of the memory; and a timing adjustment circuit configured to adjust a timing at which data is written into the memory based on a read first pattern.
Public/Granted literature
- US20120307575A1 MEMORY CONTROLLER AND CONTROL METHOD Public/Granted day:2012-12-06
Information query
