Invention Grant
US08707122B1 Nonvolatile memory controller with two-stage error correction technique for enhanced reliability
有权
具有两级纠错技术的非易失性存储器控制器，增强可靠性
- Patent Title: Nonvolatile memory controller with two-stage error correction technique for enhanced reliability
- Patent Title (中): 具有两级纠错技术的非易失性存储器控制器，增强可靠性
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Application No.: US13023336Application Date: 2011-02-08
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Publication No.: US08707122B1Publication Date: 2014-04-22
- Inventor: Rino Micheloni , Peter Z. Onufryk , Alessia Marelli , Christopher I. W. Norrie
- Applicant: Rino Micheloni , Peter Z. Onufryk , Alessia Marelli , Christopher I. W. Norrie
- Applicant Address: US CA Sunnyvale
- Assignee: PMC-Sierra US, Inc.
- Current Assignee: PMC-Sierra US, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Glass & Associates
- Agent Kenneth Glass; Stanley J. Pawlik
- Main IPC: H03M13/00
- IPC: H03M13/00
Abstract:
A nonvolatile memory controller generates an error correction code for each data unit in a data stripe and generates a parity unit based on the data units of the data stripe. If a data unit of the data stripe has a number of data bit errors not exceeding the error correction capacity of the nonvolatile memory controller, the nonvolatile memory controller corrects any data bit errors in the data unit based on the error correction code of the data unit. Otherwise, if a data unit of the data stripe has a number of data bit error exceeding the error correction capacity of the nonvolatile memory controller, the nonvolatile memory controller recovers the data unit based on the other data units of the data stripe and the parity unit.
Information query
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