Invention Grant
US08707231B2 Method and system for derived layer checking for semiconductor device design
有权
用于半导体器件设计的导出层检查的方法和系统
- Patent Title: Method and system for derived layer checking for semiconductor device design
- Patent Title (中): 用于半导体器件设计的导出层检查的方法和系统
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Application No.: US13562443Application Date: 2012-07-31
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Publication No.: US08707231B2Publication Date: 2014-04-22
- Inventor: Douglas M. Reber , Mehul D. Shroff , Edward O. Travis
- Applicant: Douglas M. Reber , Mehul D. Shroff , Edward O. Travis
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Jonathan N. Geld
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F19/00 ; G03F1/00 ; G21K5/00

Abstract:
A system and method are provided for enabling a systematic detection of issues arising during the course of mask generation for a semiconductor device. IC mask layer descriptions are analyzed and information is generated that identifies devices formed by active layers in the masks, along with a description of all layers in proximity to the found devices. The IC mask information is compared to a netlist file generated from the initial as-designed schematic. Determinations can then made, for example, as to whether all intended devices are present, any conflicting layers are in proximity to or interacting with the intended devices, and any unintended devices are present in the mask layers. Steps can then be taken to resolve the issues presented by the problematic devices.
Public/Granted literature
- US20140040839A1 METHOD AND SYSTEM FOR DERIVED LAYER CHECKING FOR SEMICONDUCTOR DEVICE DESIGN Public/Granted day:2014-02-06
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