Invention Grant
- Patent Title: Automatic misalignment balancing scheme for multi-patterning technology
- Patent Title (中): 多图案化技术的自动对准平衡方案
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Application No.: US13562436Application Date: 2012-07-31
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Publication No.: US08709684B2Publication Date: 2014-04-29
- Inventor: Chan-Hong Chern , Tao Wen Chung , Ming-Chieh Huang , Chih-Chang Lin , Tsung-Ching (Jim) Huang , Fu-Lung Hsueh
- Applicant: Chan-Hong Chern , Tao Wen Chung , Ming-Chieh Huang , Chih-Chang Lin , Tsung-Ching (Jim) Huang , Fu-Lung Hsueh
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Associates, LLC
- Main IPC: G03F1/68
- IPC: G03F1/68

Abstract:
Some aspects of the present disclosure provide for a method of automatically balancing mask misalignment for multiple patterning layers to minimize the consequences of mask misalignment. In some embodiments, the method defines a routing grid for one or more double patterning layers within an IC layout. The routing grid has a plurality of vertical grid lines extending along a first direction and a plurality of horizontal grid lines extending along a second, orthogonal direction. Alternating lines of the routing grid in a given direction (e.g., the horizontal and vertical direction) are assigned different colors. Shapes on the double patterning layers are then routed along the routing grid in a manner that alternates between different colored grid lines. By routing in such a manner, variations in capacitive coupling caused by mask misalignment are reduced.
Public/Granted literature
- US20140038085A1 Automatic Misalignment Balancing Scheme for Multi-Patterning Technology Public/Granted day:2014-02-06
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