The control circuit selects, as the first reference cell, the first memory cell having a maximum reading current supplied by turning on the first select transistor in a state in which resistance values of the first memory cells are all increased. The control circuit selects, as the second reference cell, the second memory cell having a maximum reading current supplied by turning on the second select transistor in a state in which resistance values of the second memory cells are all increased. The first reference-current setting circuit sets, as the first reference current, a current obtained by adding a first adjusting current to the reading current of the first reference cell. The second reference-current setting circuit sets, as the second reference current, a current obtained by adding a second adjusting current to the reading current of the second reference cell.