An integrated circuit includes samplers, a phase error determination circuit, and periodic signal generators. The samplers generate respective sampled signals by sampling respective input signals in response to respective periodic signals. The input signals have a common phase error. The phase error determination circuit receives the sampled signals from the samplers. The phase error determination circuit generates a representation of the common phase error of the input signals in response to sampled signals received in a set-up mode in which the samplers sample respective input signals having a common bit pattern. The periodic signal generators generate the periodic signals differing in phase from one another by defined phase differences in the set-up mode and subject the periodic signals to a common phase shift in a normal mode in response to the representation of the common phase error. The common phase shift matches the common phase error of the input signals.