Invention Grant
- Patent Title: Aware manufacturing of integrated circuits
- Patent Title (中): 意识到集成电路制造
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Application No.: US12731118Application Date: 2010-03-24
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Publication No.: US08713484B2Publication Date: 2014-04-29
- Inventor: Louis K. Scheffer , Akira Fujimura
- Applicant: Louis K. Scheffer , Akira Fujimura
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Adeli LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G03F1/00 ; G03F7/00

Abstract:
Some embodiments of the invention provide a manufacturing aware process for designing an integrated circuit (“IC”) layout. The process receives a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture an IC based on the IC layout. The process defines a set of design rules based on the specified manufacturing configuration. The process uses the set of design rules to design the IC layout. Some embodiments of the invention provide a design aware process for manufacturing an integrated circuit (“IC”). The process receives an IC design with an associated set of design properties. The process specifies a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture the IC, where the specified set of manufacturing settings are based on the set of design properties. The process manufactures the IC based on the manufacturing settings.
Public/Granted literature
- US20100180247A1 AWARE MANUFACTURING OF INTEGRATED CIRCUITS Public/Granted day:2010-07-15
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