Invention Grant
- Patent Title: Combined conductive plug/conductive line memory arrays and methods of forming the same
- Patent Title (中): 组合导电插头/导线存储器阵列及其形成方法
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Application No.: US13364382Application Date: 2012-02-02
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Publication No.: US08716059B2Publication Date: 2014-05-06
- Inventor: Roberto Somaschini , Fabio Pellizzer , Carmela Cupeta , Nicola Nastasi
- Applicant: Roberto Somaschini , Fabio Pellizzer , Carmela Cupeta , Nicola Nastasi
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Brooks, Cameron & Huebsch, PLLC
- Main IPC: H01L29/02
- IPC: H01L29/02
Abstract:
Memory arrays and methods of forming the same are provided. One example method of forming a memory array can include forming a conductive material in a number of vias and on a substrate structure, the conductive material to serve as a number of conductive lines of the array and coupling the number of conductive lines to the array circuitry.
Public/Granted literature
- US20130200322A1 MEMORY ARRAYS AND METHODS OF FORMING THE SAME Public/Granted day:2013-08-08
Information query
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