Invention Grant
- Patent Title: MOS transistors having reduced leakage well-substrate junctions
- Patent Title (中): MOS晶体管具有减少的泄漏良好的衬底结
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Application No.: US13584016Application Date: 2012-08-13
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Publication No.: US08716097B2Publication Date: 2014-05-06
- Inventor: Terry James Bordelon, Jr. , Amitava Chatterjee
- Applicant: Terry James Bordelon, Jr. , Amitava Chatterjee
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H01L21/20
- IPC: H01L21/20 ; H01L29/93

Abstract:
A Metal-Oxide Semiconductor (MOS) transistor includes a substrate having a topside semiconductor surface doped with a first dopant type having a baseline doping level. A well is formed in the semiconductor surface doped with a second doping type. The well forms a well-substrate junction having a well depletion region. A retrograde doped region is below the well-substrate junction doped with the first dopant type having a peak first dopant concentration of between five (5) and one hundred (100) times above the baseline doping level at a location of the peak first dopant concentration, wherein with zero bias across the well-substrate junction at least (>) ninety (90) % of a total dose of the retrograde doped region is below the bottom of the well depletion region. A gate structure is on the well. Source and drain regions are on opposing sides of the gate structure.
Public/Granted literature
- US20140042545A1 MOS TRANSISTORS HAVING REDUCED LEAKAGE WELL-SUBSTRATE JUNCTIONS Public/Granted day:2014-02-13
Information query
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