Invention Grant
- Patent Title: SOI lateral MOSFET devices
- Patent Title (中): SOI横向MOSFET器件
-
Application No.: US13131779Application Date: 2010-08-10
-
Publication No.: US08716794B2Publication Date: 2014-05-06
- Inventor: Xiaorong Luo , Florin Udrea
- Applicant: Xiaorong Luo , Florin Udrea
- Applicant Address: CN Chengdu, Sichuan Province
- Assignee: University of Electronic Science and Technology of China
- Current Assignee: University of Electronic Science and Technology of China
- Current Assignee Address: CN Chengdu, Sichuan Province
- Agency: Casimir Jones SC
- Priority: CN201010173833 20100517
- International Application: PCT/CN2010/075849 WO 20100810
- International Announcement: WO2011/143848 WO 20111124
- Main IPC: H01L29/78
- IPC: H01L29/78
Abstract:
The present invention relates to a semiconductor power device and power integrated circuits (ICs). The lateral SOI MOSFET in the present comprises a trench gate extended to the dielectric buried layer, one or multiple dielectric trenches in the drift region, and a buried gate in said dielectric trench. The permittivity of the dielectric in said dielectric trench is lower than that of said active layer. Firstly, said dielectric trench not only greatly improves breakdown voltage, but also reduces pitch size. Secondly, the trench gate widens the effective conductive region in the vertical direction. Thirdly, dual gates of said trench gate and buried gate increase channel and current densities. Thereby, specific on-resistance and the power loss are reduced. The device of the present invention has many advantages, such as high voltage, high speed, low power loss, low cost and ease of integration. The device in the present invention is particularly suitable for power integrated circuits and RF power integrated circuits.
Public/Granted literature
- US20130193509A1 SOI LATERAL MOSFET DEVICES Public/Granted day:2013-08-01
Information query
IPC分类:
