Invention Grant
- Patent Title: Methods of channel stress engineering and structures formed thereby
- Patent Title (中): 通道应力工程及其结构的方法
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Application No.: US13458198Application Date: 2012-04-27
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Publication No.: US08716806B2Publication Date: 2014-05-06
- Inventor: Oleg Golonzka , Hemant Deshpande , Ajay K Sharma , Cory Weber , Ashutosh Ashutosh
- Applicant: Oleg Golonzka , Hemant Deshpande , Ajay K Sharma , Cory Weber , Ashutosh Ashutosh
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Forefront IP Lawgroup, PLLC
- Main IPC: H01L21/70
- IPC: H01L21/70
Abstract:
Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a source/drain region in an NMOS portion of a substrate, wherein the source/drain region of the NMOS portion comprises at least one dislocation, and wherein a PMOS source/drain region in a PMOS portion of the substrate does not comprise a dislocation.
Public/Granted literature
- US20120211839A1 METHODS OF CHANNEL STRESS ENGINEERING AND STRUCTURES FORMED THEREBY Public/Granted day:2012-08-23
Information query
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