Invention Grant
US08716858B2 Bump structure with barrier layer on post-passivation interconnect
有权
在钝化后互连上具有阻挡层的凹凸结构
- Patent Title: Bump structure with barrier layer on post-passivation interconnect
- Patent Title (中): 在钝化后互连上具有阻挡层的凹凸结构
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Application No.: US13167946Application Date: 2011-06-24
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Publication No.: US08716858B2Publication Date: 2014-05-06
- Inventor: Chen-Fa Lu , Chung-Shi Liu , Mirng-Ji Lii , Chen-Hua Yu
- Applicant: Chen-Fa Lu , Chung-Shi Liu , Mirng-Ji Lii , Chen-Hua Yu
- Applicant Address: TW
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW
- Agency: Lowe Hauptman & Ham, LLP
- Main IPC: H01L23/48
- IPC: H01L23/48
Abstract:
A semiconductor device includes a barrier layer between a solder bump and a post-passivation interconnect (PPI) layer. The barrier layer is formed of at least one of an electroless nickel (Ni) layer, an electroless palladium (Pd) layer or an immersion gold (Au) layer.
Public/Granted literature
- US20120326298A1 BUMP STRUCTURE WITH BARRIER LAYER ON POST-PASSIVATION INTERCONNECT Public/Granted day:2012-12-27
Information query
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