Invention Grant
- Patent Title: Low dropout voltage regulator including a bias control circuit
- Patent Title (中): 低压差稳压器包括偏置控制电路
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Application No.: US13291397Application Date: 2011-11-08
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Publication No.: US08716993B2Publication Date: 2014-05-06
- Inventor: Petr Kadanka
- Applicant: Petr Kadanka
- Applicant Address: US AZ Phoenix
- Assignee: Semiconductor Components Industries, LLC
- Current Assignee: Semiconductor Components Industries, LLC
- Current Assignee Address: US AZ Phoenix
- Agency: Polansky & Associates, P.L.L.C.
- Agent Paul J. Polensky
- Main IPC: G05F1/00
- IPC: G05F1/00 ; G05F1/56 ; G05F1/563 ; G05F1/565

Abstract:
A low dropout (LDO) regulator includes a voltage regulation loop for providing an output voltage to an output terminal, where the output voltage is proportional to a reference voltage. The voltage regulation loop includes a current bias input for receiving a bias current. The LDO regulator also includes a bias current control circuit for providing the bias current at a first value when the reference voltage is greater than a feedback voltage and at a second value higher than the first value when the reference voltage is less than the feedback voltage.
Public/Granted literature
- US20130113447A1 LOW DROPOUT VOLTAGE REGULATOR INCLUDING A BIAS CONTROL CIRCUIT Public/Granted day:2013-05-09
Information query
IPC分类: