Invention Grant
- Patent Title: Programmable logic device with a self-power down mechanism
- Patent Title (中): 具有自省电机制的可编程逻辑器件
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Application No.: US13353246Application Date: 2012-01-18
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Publication No.: US08717062B2Publication Date: 2014-05-06
- Inventor: Chee Wai Yap
- Applicant: Chee Wai Yap
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Womble Carlyle Sandridge & Rice LLP
- Main IPC: H03K19/177
- IPC: H03K19/177

Abstract:
Apparatuses for reducing power consumption in a programmable logic device (PLD) with a self power down mechanism are disclosed. Methods and a machine readable medium for restoring a prior known state are provided. The prior known state is stored in a memory module before the PLD is powered down and the same state is restored from the memory module when the PLD is powered up. The memory module may be an internal or an external non-volatile or volatile memory source. One sector of the memory may be used to store the previous known state. The memory sector can be partitioned into different sections. One section may be used as a header section associated with a data storage section. Partitioning the memory sector into different sections and utilizing multiple addresses from each section ensure less read and write cycles during the powering down and the powering up of the PLD.
Public/Granted literature
- US20120112789A1 PROGRAMMABLE LOGIC DEVICE WITH A SELF-POWER DOWN MECHANISM Public/Granted day:2012-05-10
Information query
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