Invention Grant
- Patent Title: Layout for semiconductor memories
- Patent Title (中): 半导体存储器布局
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Application No.: US13242399Application Date: 2011-09-23
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Publication No.: US08717798B2Publication Date: 2014-05-06
- Inventor: Jhon Jhy Liaw
- Applicant: Jhon Jhy Liaw
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Main IPC: G11C5/06
- IPC: G11C5/06

Abstract:
A semiconductor memory includes a first conductive layer including a first pair of bit lines coupled to a first bit cell and a second conductive layer including a second pair of bit lines coupled to the first bit cell. The first and second conductive layers are vertically separated from each other.
Public/Granted literature
- US20130077375A1 LAYOUT FOR SEMICONDUCTOR MEMORIES Public/Granted day:2013-03-28
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