Invention Grant
- Patent Title: Memory device and corresponding reading method
- Patent Title (中): 内存设备及相应的阅读方式
-
Application No.: US13331396Application Date: 2011-12-20
-
Publication No.: US08717825B2Publication Date: 2014-05-06
- Inventor: Cesare Torti
- Applicant: Cesare Torti
- Applicant Address: IT Agrate Brianza (MB)
- Assignee: STMicroelectronics S.R.L.
- Current Assignee: STMicroelectronics S.R.L.
- Current Assignee Address: IT Agrate Brianza (MB)
- Agency: Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.
- Priority: ITMI2010A2343 20101221
- Main IPC: G11C11/40
- IPC: G11C11/40

Abstract:
An electrically erasable and programmable non-volatile memory device includes memory cells arranged in rows and columns, and each column of memory cells is associated with a respective local bit line. The local bit lines are divided into packets of local bit lines, each packet of local bit lines associated with a respective main bit line. Each local bit line is selectively couplable to the respective main bit line by a corresponding selector. Each local bit line is selectively couplable to a reference terminal, for receiving a reference voltage, by a corresponding discharge selector. Each discharge selector is active when the memory device is in a standby state. The non-volatile memory device further includes biasing circuitry to bias each main bit line to a pre-charge voltage during operation, and reading circuitry to select and access a group of memory cells during reading operations.
Public/Granted literature
- US20120155185A1 MEMORY DEVICE AND CORRESPONDING READING METHOD Public/Granted day:2012-06-21
Information query