Aspects of the disclosure provide a memory module including at least one memory block. The memory block includes a memory array and a shift wrapper. The memory array includes regular cell lines and at least a redundant cell line. The regular cell lines and the redundant cell line extend in a bit-line direction, and are ordered in a word-line direction. The shift wrapper interfaces between block inputs/outputs and the regular and redundant cell lines. The shift wrapper is configured to shift a mapping between the block inputs/outputs and the regular and redundant cell lines to bypass a defective cell line that has at least one defective cell, and engage the redundant cell line, while maintaining the order in the word-line direction.