Invention Grant
- Patent Title: Semiconductor device having plural penetration electrodes penetrating through semiconductor substrate and testing method thereof
- Patent Title (中): 具有穿透半导体衬底的多个穿透电极的半导体器件及其测试方法
-
Application No.: US13398702Application Date: 2012-02-16
-
Publication No.: US08717839B2Publication Date: 2014-05-06
- Inventor: Hideyuki Yokou , Yasuyuki Shigezane
- Applicant: Hideyuki Yokou , Yasuyuki Shigezane
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Tokyo
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2011-035684 20110222
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G11C5/06 ; G11C7/06 ; G11C7/10 ; G11C29/02

Abstract:
Disclosed herein is a device that includes first and second current paths, first and second latch circuits electrically connected to the first and second current paths, respectively, a driver circuit supplying first data to the first latch circuit, and supplying second data representing a logical value opposite to a logical value of the first data to the second latch circuit, a control circuit controlling the driver circuit to be alternately and repeatedly in a first period in which the driver circuit supplies the first data to the first latch circuit and does not supply the second data to the second latch circuit, and in a second period in which the driver circuit supplies the second data to the second latch circuit and does not supply the first data to the first latch circuit, and a monitor circuit.
Public/Granted literature
Information query