Invention Grant
US08717882B2 Repurposing data lane as clock lane by migrating to reduced speed link operation
有权
通过迁移到降低速度链路操作来重新定位数据通道作为时钟通道
- Patent Title: Repurposing data lane as clock lane by migrating to reduced speed link operation
- Patent Title (中): 通过迁移到降低速度链路操作来重新定位数据通道作为时钟通道
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Application No.: US13175798Application Date: 2011-07-01
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Publication No.: US08717882B2Publication Date: 2014-05-06
- Inventor: Venkatraman Iyer , Robert G. Blankenship , Allen J. Baum
- Applicant: Venkatraman Iyer , Robert G. Blankenship , Allen J. Baum
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Caven & Aghevli LLC
- Main IPC: H04J3/06
- IPC: H04J3/06
Abstract:
Methods and apparatus relating to repurposing a data lane as a clock lane by migrating to reduced speed link operation are described. In one embodiment, speed of a link is reduced upon detection of failure on a clock lane of the link and one of a plurality of data lanes of a link is repurposed as a replacement clock lane. Other embodiments are also disclosed and claimed.
Public/Granted literature
- US20130007502A1 REPURPOSING DATA LANE AS CLOCK LANE BY MIGRATING TO REDUCED SPEED LINK OPERATION Public/Granted day:2013-01-03
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