Invention Grant
- Patent Title: Reduced complexity viterbi decoding
- Patent Title (中): 降低复杂性维特比解码
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Application No.: US12538570Application Date: 2009-08-10
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Publication No.: US08718202B2Publication Date: 2014-05-06
- Inventor: Rami Abdallah , Seok-Jun Lee , Manish Goel
- Applicant: Rami Abdallah , Seok-Jun Lee , Manish Goel
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Steven A. Shaw; Wade James Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H04L27/06
- IPC: H04L27/06 ; H04L27/28 ; H03M13/41
Abstract:
A system includes a Viterbi decoder. The Viterbi decoder includes add compare select logic. The add compare select logic determines path metrics for an encoded signal. The add compare select logic also is shared to determine a best state by which trace-back procedure gets started, resulting in hardware saving.
Public/Granted literature
- US20100034324A1 REDUCED COMPLEXITY VITERBI DECODING Public/Granted day:2010-02-11
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