Invention Grant
- Patent Title: Signal wiring system and jitter suppression circuit
- Patent Title (中): 信号线路系统和抖动抑制电路
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Application No.: US13403124Application Date: 2012-02-23
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Publication No.: US08718214B2Publication Date: 2014-05-06
- Inventor: Yasushi Aoki
- Applicant: Yasushi Aoki
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Sughrue Mion, PLLC
- Priority: JP2011-044895 20110302
- Main IPC: H04L25/00
- IPC: H04L25/00

Abstract:
Reducing jitter in signal wiring without requiring a larger circuit scale is difficult in the technology of the related art. A signal wiring system to resolve the above problem therefore includes an output unit to output a differential signal, a receiver unit to receive differential signals from the output unit, a jitter suppression circuit to suppress the amount of the jitter in the differential signal received by the receiver unit according to a suppression coefficient, and a signal wiring unit for conveying a differential signal from the output unit and including a wiring length set according to a suppression coefficient in the jitter suppression circuit.
Public/Granted literature
- US20120224656A1 SIGNAL WIRING SYSTEM AND JITTER SUPPRESSION CIRCUIT Public/Granted day:2012-09-06
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