Invention Grant
US08719613B2 Single-wire serial interface with delay module for full clock rate data communication between master and slave devices
有权
具有延迟模块的单线串行接口，用于主设备和从设备之间的全时钟速率数据通信
- Patent Title: Single-wire serial interface with delay module for full clock rate data communication between master and slave devices
- Patent Title (中): 具有延迟模块的单线串行接口，用于主设备和从设备之间的全时钟速率数据通信
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Application No.: US13013625Application Date: 2011-01-25
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Publication No.: US08719613B2Publication Date: 2014-05-06
- Inventor: Gary Neben
- Applicant: Gary Neben
- Applicant Address: US TX Plano
- Assignee: Futurewei Technologies, Inc.
- Current Assignee: Futurewei Technologies, Inc.
- Current Assignee Address: US TX Plano
- Agency: Conley Rose, P.C.
- Agent Grant Rodolph; Nicholas K. Beaulieu
- Main IPC: G06F1/12
- IPC: G06F1/12 ; G06F13/42 ; G06F5/00 ; G06F7/00 ; H04L7/00 ; H04L25/00
Abstract:
A circuit comprising a single-wire serial interface (SWSI), a delay module coupled to the SWSI and operable to introduce a delay during a data transmission, the delay being dependent on a local clock (LC) associated with the circuit, wherein the delay enables the circuit to synchronize the data transmission with a device coupled to the SWSI based on the LC.
Public/Granted literature
- US20110185215A1 Single-Wire Serial Interface Public/Granted day:2011-07-28
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