Invention Grant
US08719646B2 Non-volatile memory (NVM) reset sequence with built-in read check
有权
非易失性存储器（NVM）复位序列具有内置读取检查功能
- Patent Title: Non-volatile memory (NVM) reset sequence with built-in read check
- Patent Title (中): 非易失性存储器（NVM）复位序列具有内置读取检查功能
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Application No.: US13459500Application Date: 2012-04-30
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Publication No.: US08719646B2Publication Date: 2014-05-06
- Inventor: Chen He , Kelly K. Taylor
- Applicant: Chen He , Kelly K. Taylor
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Main IPC: G11C29/00
- IPC: G11C29/00
Abstract:
A new, robust non-volatile memory (NVM) reset sequence is provided in accordance with at least one embodiment, which, after reading a Test NVM portion and overwriting NVM configuration registers' default values with the values read from the Test NVM portion, does a read integrity check. If the read integrity check passes, a reset process will conclude. Otherwise, if the read integrity check fails, the reset process will re-try reading the Test NVM and overwriting the NVM configuration registers' default values. If the read integrity check still fails after a maximum number of re-tries, a fail flag will be set, and the predetermined “safe” default values will be reloaded to the NVM configuration registers, thereby assuring that the NVM device is operational.
Public/Granted literature
- US20130290797A1 NON-VOLATILE MEMORY (NVM) RESET SEQUENCE WITH BUILT-IN READ CHECK Public/Granted day:2013-10-31
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