Invention Grant
US08719647B2 Read bias management to reduce read errors for phase change memory
有权
读取偏差管理以减少相变存储器的读取错误
- Patent Title: Read bias management to reduce read errors for phase change memory
- Patent Title (中): 读取偏差管理以减少相变存储器的读取错误
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Application No.: US13327673Application Date: 2011-12-15
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Publication No.: US08719647B2Publication Date: 2014-05-06
- Inventor: Ferdinando Bedeschi
- Applicant: Ferdinando Bedeschi
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Knobbe, Martens, Olson & Bear, LLP
- Main IPC: G11C29/00
- IPC: G11C29/00

Abstract:
Subject matter disclosed herein relates to a memory device, and more particularly to read performance of phase change memory. During a reading process, a bias condition can be applied to a memory cell to determine the memory cell's state. The determined state of the memory cell can depend on a threshold voltage of the memory cell. The threshold voltage of the memory cell may shift over time. The shift in threshold voltage may result in read errors. The applied bias condition may be modified based on the resulting read errors.
Public/Granted literature
- US20130159796A1 READ BIAS MANAGEMENT TO REDUCE READ ERRORS FOR PHASE CHANGE MEMORY Public/Granted day:2013-06-20
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