Invention Grant
- Patent Title: Scan chain diagnostic using scan stitching
- Patent Title (中): 扫描链诊断使用扫描缝合
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Application No.: US13330466Application Date: 2011-12-19
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Publication No.: US08719651B1Publication Date: 2014-05-06
- Inventor: Nilabha Dev , Sameer Chakravarthy Chillarige , Shaleen Bhabu
- Applicant: Nilabha Dev , Sameer Chakravarthy Chillarige , Shaleen Bhabu
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Kenyon & Kenyon LLP
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G06F11/00

Abstract:
An apparatus and method for generating scan chain connections for an integrated circuit (IC) in order to perform scan diagnosis of a manufactured IC chip, in which the scan chain connections are determined using functional path information among the flip flops of the IC design corresponding to the IC chip. A plurality of flip flops included in the IC is grouped into at least a first group and a second group based on the functional path information among the flip flops. At least one scan chain is generated from at least a portion of the flip flops in the first group. At least one scan chain is generated from at least a portion of the flip flops in the second group.
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