Invention Grant
US08719754B1 System and method to generate re-useable layout components from schematic components in an IC design with hierarchical parameters
有权
从具有分层参数的IC设计中的原理图组件生成可重复使用的布局组件的系统和方法
- Patent Title: System and method to generate re-useable layout components from schematic components in an IC design with hierarchical parameters
- Patent Title (中): 从具有分层参数的IC设计中的原理图组件生成可重复使用的布局组件的系统和方法
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Application No.: US13750659Application Date: 2013-01-25
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Publication No.: US08719754B1Publication Date: 2014-05-06
- Inventor: Arnold Ginetti
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Kenyon & Kenyon LLP
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A method is provided to align poly features within chain sets in an integrated circuit layout design stored in a non-transitory computer readable storage device comprising: vertically aligning a first poly feature of a first pcell instance in a first chain set with a second poly feature of a second pcell instance in a second chain set; configuring a computer to, starting with the aligned first and second poly features, successively determine multiple changed poly feature spacing values associated with at least one of the first and second pcell instances to align successive poly features in chain order in a first horizontal direction; and assigning respective determined changed poly feature spacing values to their associated first or second pcell instances.
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