Invention Grant
US08719760B1 Validating integrated circuit simulation results 有权
验证集成电路仿真结果

Validating integrated circuit simulation results
Abstract:
A technique validates results from a circuit simulation estimation program. The technique determines whether the estimated results satisfy Kirchhoff's current law (KCL), Kirchhoff's voltage laws (KVL), and power conservation for the original circuit. A reporting tool shows the validation results and may be customized by the user. The tool can show in the original circuitry where the estimated results may be inaccurate.
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