Invention Grant
- Patent Title: Methods of forming 3-D circuits with integrated passive devices
- Patent Title (中): 用集成无源器件形成3-D电路的方法
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Application No.: US13731242Application Date: 2012-12-31
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Publication No.: US08722459B2Publication Date: 2014-05-13
- Inventor: Paul W. Sanders , Robert E. Jones , Michael F. Petras
- Applicant: Freescale Semiconductor, Inc.
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Sherry W. Schumm
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrate-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so that TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TSVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing.
Public/Granted literature
- US20130143367A1 METHODS OF FORMING 3-D CIRCUITS WITH INTEGRATED PASSIVE DEVICES Public/Granted day:2013-06-06
Information query
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