Reduced topography in isolation regions of a semiconductor device by applying a deposition/etch sequence prior to forming the interlayer dielectric

Invention Grant

US08722511B2 Reduced topography in isolation regions of a semiconductor device by applying a deposition/etch sequence prior to forming the interlayer dielectric 有权

Title translation: 通过在形成层间电介质之前施加沉积/蚀刻顺序来减少半导体器件的隔离区域的形貌

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Patent Title: Reduced topography in isolation regions of a semiconductor device by applying a deposition/etch sequence prior to forming the interlayer dielectric
Patent Title (中): 通过在形成层间电介质之前施加沉积/蚀刻顺序来减少半导体器件的隔离区域的形貌
Application No.: US13154754

Application Date: 2011-06-07
Publication No.: US08722511B2

Publication Date: 2014-05-13
Inventor: Ralf Richter , Peter Javorka , Kai Frohberg
Applicant: Ralf Richter , Peter Javorka , Kai Frohberg
Applicant Address: KY Grand Cayman
Assignee: GLOBALFOUNDRIES Inc.
Current Assignee: GLOBALFOUNDRIES Inc.
Current Assignee Address: KY Grand Cayman
Agency: Amerson Law Firm, PLLC
Priority: DE102010038746 20100730
Main IPC: H01L21/76
IPC: H01L21/76

Reduced topography in isolation regions of a semiconductor device by applying a deposition/etch sequence prior to forming the interlayer dielectric

Abstract:

Contact failures in sophisticated semiconductor devices may be reduced by relaxing the pronounced surface topography in isolation regions prior to depositing the interlayer dielectric material system. To this end, a deposition/etch sequence may be applied in which a fill material may be removed from the active region, while the recesses in the isolation regions may at least be partially filled.

Abstract(Chinese):

复杂的半导体器件中的接触故障可以通过在沉积层间绝缘材料系统之前放宽隔离区域中显着的表面形貌来降低。为此，可以施加沉积/蚀刻顺序，其中填充材料可以从有源区域移除，而隔离区域中的凹部可以至少部分地被填充。

Public/Granted literature

US20120025318A1 Reduced Topography in Isolation Regions of a Semiconductor Device by Applying a Deposition/Etch Sequence Prior to Forming the Interlayer Dielectric Public/Granted day:2012-02-02

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/71	..限定在组H01L21／70中的器件的特殊部件的制造（H01L21/28，H01L21/44，H01L21/48优先）
H01L21/76	...组件间隔离区的制作