Invention Grant
- Patent Title: Semiconductor chip stack package and manufacturing method thereof
- Patent Title (中): 半导体芯片堆叠封装及其制造方法
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Application No.: US13391063Application Date: 2011-02-22
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Publication No.: US08722513B2Publication Date: 2014-05-13
- Inventor: Jae-Hak Lee , Chang-Woo Lee , Joon-Yub Song , Tae-Ho Ha
- Applicant: Jae-Hak Lee , Chang-Woo Lee , Joon-Yub Song , Tae-Ho Ha
- Applicant Address: KR Daejeon
- Assignee: Korea Institute of Machinery & Materials
- Current Assignee: Korea Institute of Machinery & Materials
- Current Assignee Address: KR Daejeon
- Agency: Lexyoume IP Meister, PLLC
- Priority: KR10-2010-0131939 20101221
- International Application: PCT/KR2011/001166 WO 20110222
- International Announcement: WO2012/086871 WO 20120628
- Main IPC: H01L21/30
- IPC: H01L21/30 ; H01L21/31
Abstract:
The present invention relates to a semiconductor chip stack package and a manufacturing method thereof, and more particularly, to a semiconductor chip stack package and a manufacturing method thereof in which a plurality of chips can be rapidly arranged and bonded without a precise device or operation so as to improve productivity.
Public/Granted literature
- US20130256911A1 SEMICONDUCTOR CHIP STACK PACKAGE AND MANUFACTURING METHOD THEREOF Public/Granted day:2013-10-03
Information query
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