Invention Grant
- Patent Title: Multi-tiered semiconductor devices and associated methods
- Patent Title (中): 多层半导体器件及相关方法
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Application No.: US13165546Application Date: 2011-06-21
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Publication No.: US08722525B2Publication Date: 2014-05-13
- Inventor: Nishant Sinha
- Applicant: Nishant Sinha
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman, Lundberg & Woessner, P.A.
- Main IPC: H01L21/84
- IPC: H01L21/84 ; H01L21/311 ; H01L27/06

Abstract:
Methods of fabricating multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, a first dielectric is formed, and a second dielectric is formed in contact with the first dielectric. A channel is formed through the first dielectric and the second dielectric with a first etch chemistry, a void is formed in the first dielectric with a second etch chemistry, and a device is formed at least partially in the void in the first dielectric. Additional embodiments are also described.
Public/Granted literature
- US20120326221A1 MULTI-TIERED SEMICONDUCTOR DEVICES AND ASSOCIATED METHODS Public/Granted day:2012-12-27
Information query
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