Invention Grant
US08723258B2 Electrostatic discharge (ESD) tolerance for a lateral double diffusion metal oxide semiconductor (LDMOS) transistor
有权
横向双扩散金属氧化物半导体（LDMOS）晶体管的静电放电（ESD）耐受性
- Patent Title: Electrostatic discharge (ESD) tolerance for a lateral double diffusion metal oxide semiconductor (LDMOS) transistor
- Patent Title (中): 横向双扩散金属氧化物半导体（LDMOS）晶体管的静电放电（ESD）耐受性
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Application No.: US13229201Application Date: 2011-09-09
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Publication No.: US08723258B2Publication Date: 2014-05-13
- Inventor: Kiyofumi Nakaya , Tetsuro Hirano , Shuji Fujiwara
- Applicant: Kiyofumi Nakaya , Tetsuro Hirano , Shuji Fujiwara
- Applicant Address: US AZ Phoenix
- Assignee: Semiconductor Components Industries, LLC
- Current Assignee: Semiconductor Components Industries, LLC
- Current Assignee Address: US AZ Phoenix
- Agency: Noon Intellectual Property Law, PC
- Priority: JP2010-201584 20100909
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/06 ; H01L29/78 ; H01L29/08
Abstract:
An ESD tolerance of an LDMOS transistor is improved. An N+ type source layer shaped in a ladder and having a plurality of openings in its center is formed in a surface of a P type base layer using a gate electrode and a resist mask. A P+ type contact layer is formed to be buried in the opening. At that time, a distance from an edge of the opening, that is an edge of the P+ type contact layer, to an edge of the N+ type source layer is set to a predetermined distance. The predetermined distance is equal to a distance at which an HBM+ESD tolerance of the LDMOS transistor, which increases as the distance increases, begins to saturate.
Public/Granted literature
- US20120061757A1 SEMICONDUCTOR DEVICE Public/Granted day:2012-03-15
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