Invention Grant
US08723268B2 N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch
有权
N沟道和P沟道端到端finFET单元架构，具有放宽的栅极间距
- Patent Title: N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch
- Patent Title (中): N沟道和P沟道端到端finFET单元架构，具有放宽的栅极间距
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Application No.: US13495810Application Date: 2012-06-13
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Publication No.: US08723268B2Publication Date: 2014-05-13
- Inventor: Victor Moroz , Deepak D. Sherlekar
- Applicant: Victor Moroz , Deepak D. Sherlekar
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Haynes Beffel & Wolfeld LLP
- Agent Yiding Wu
- Main IPC: H01L29/76
- IPC: H01L29/76
Abstract:
A finFET block architecture uses end-to-end finFET blocks in which the fin lengths are at least twice the contact pitch, whereby there is enough space for interlayer connectors to be placed on the proximal end and the distal end of a given semiconductor fin, and on the gate element on the given semiconductor fin. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. Interlayer connectors can be aligned over corresponding semiconductor fins which connect to gate elements.
Public/Granted literature
- US20130334610A1 N-CHANNEL AND P-CHANNEL END-TO-END FINFET CELL ARCHITECTURE WITH RELAXED GATE PITCH Public/Granted day:2013-12-19
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