Invention Grant
US08726113B2 Selective per-cycle masking of scan chains for system level test
有权
用于系统级测试的扫描链选择性每周期屏蔽
- Patent Title: Selective per-cycle masking of scan chains for system level test
- Patent Title (中): 用于系统级测试的扫描链选择性每周期屏蔽
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Application No.: US13453929Application Date: 2012-04-23
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Publication No.: US08726113B2Publication Date: 2014-05-13
- Inventor: Janusz Rajski , Dariusz Czysz , Grzegorz Mrugalski , Nilanjan Mukherjee , Jerzy Tyszer
- Applicant: Janusz Rajski , Dariusz Czysz , Grzegorz Mrugalski , Nilanjan Mukherjee , Jerzy Tyszer
- Applicant Address: US OR Wilsonville
- Assignee: Mentor Graphics Corporation
- Current Assignee: Mentor Graphics Corporation
- Current Assignee Address: US OR Wilsonville
- Agency: Klarquist Sparkman, LLP
- Main IPC: G01R31/28
- IPC: G01R31/28
Abstract:
Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.
Public/Granted literature
- US20120210181A1 SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST Public/Granted day:2012-08-16
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