Invention Grant
US08726736B2 Method for determining the local stress induced in a semiconductor material wafer by through vias
有权
用于通过通孔确定在半导体材料晶片中引起的局部应力的方法
- Patent Title: Method for determining the local stress induced in a semiconductor material wafer by through vias
- Patent Title (中): 用于通过通孔确定在半导体材料晶片中引起的局部应力的方法
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Application No.: US13524699Application Date: 2012-06-15
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Publication No.: US08726736B2Publication Date: 2014-05-20
- Inventor: Mohamed Bouchoucha , Pascal Chausse , Laurent-Luc Chapelon
- Applicant: Mohamed Bouchoucha , Pascal Chausse , Laurent-Luc Chapelon
- Applicant Address: FR Crolles FR Paris
- Assignee: STMicroelectronics (Crolles 2) SAS,Commissariat à l'Énergie Atomique et aux Énergies Alternatives
- Current Assignee: STMicroelectronics (Crolles 2) SAS,Commissariat à l'Énergie Atomique et aux Énergies Alternatives
- Current Assignee Address: FR Crolles FR Paris
- Agency: Wolf, Greenfield & Sacks, P.C.
- Priority: FR1155877 20110630
- Main IPC: G01B5/00
- IPC: G01B5/00
Abstract:
A method for determining, in a first semiconductor material wafer having at least one through via, mechanical stress induced by the at least one through via, this method including the steps of: manufacturing a test structure from a second wafer of the same nature as the first wafer, in which the at least one through via is formed by a substantially identical method, a rear surface layer being further arranged on this second wafer so that the via emerges on the layer; measuring the mechanical stress in the rear surface layer; and deducing therefrom the mechanical stress induced in the first semiconductor material wafer.
Public/Granted literature
- US20130112974A1 METHOD FOR DETERMINING THE LOCAL STRESS INDUCED IN A SEMICONDUCTOR MATERIAL WAFER BY THROUGH VIAS Public/Granted day:2013-05-09
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