Invention Grant
- Patent Title: Methods of patterning small via pitch dimensions
- Patent Title (中): 通过间距尺寸图案化的方法
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Application No.: US13465343Application Date: 2012-05-07
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Publication No.: US08728332B2Publication Date: 2014-05-20
- Inventor: Chung-Yi Lin , Jiing-Feng Yang , Tzu-Hao Huang , Chih-Hao Hsieh , Dian-Hau Chen , Hsiang-Lin Chen , Ko-Bin Kao , Yung-Shih Cheng
- Applicant: Chung-Yi Lin , Jiing-Feng Yang , Tzu-Hao Huang , Chih-Hao Hsieh , Dian-Hau Chen , Hsiang-Lin Chen , Ko-Bin Kao , Yung-Shih Cheng
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01B13/00
- IPC: H01B13/00

Abstract:
Integrated circuit methods are described. The methods include providing a photomask that includes two main features for two via openings and further includes an optical proximity correction (OPC) feature linking the two main features; forming a hard mask layer on a substrate, the hard mask layer including two trench openings; forming a patterned resist layer over the hard mask layer using the photomask, wherein the patterned resist layer includes a peanut-shaped opening with two end portion aligned with the two trench openings of the hard mask layer, respectively; and performing a first etch process to the substrate using the hard mask layer and the patterned resist layer as a combined etch mask.
Public/Granted literature
- US20130295769A1 METHODS OF PATTERNING SMALL VIA PITCH DIMENSIONS Public/Granted day:2013-11-07
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